Development of Cap Layers for High Temperature Pulse Annealing of GaN

I. Ostermay, N. Thiele, A. Koyucuoglu, P. Paul, A. Bassal, A. Thies, F. Brunner and O. Krueger

Published in:

International Conference on Compound Semiconductor Manufacturing Technology (CS ManTech 2025), New Orleans, USA, May 19-22, paper 12.17 (2025).

Abstract:

For high-performance GaN-based transistors, minimizing contact resistance is essential to reduce power losses and enhance switching efficiency. Achieving highly-doped contact areas in GaN is challenging due to its high binding energy and self-compensation effects. This study investigates the electrical activation of silicon-implanted GaN-on-sapphire structures using rapid thermal annealing (RTA) and optimized cap layers. Various cap materials, including sputtered and PECVD SiN_x, Al₂O₃, and bilayer approaches, were evaluated for their ability to prevent GaN decomposition during high-temperature annealing. The best-performing cap consisted of a 10 nm thick CVD SiN_x layer followed by 10 nm ALD Al₂O₃ layer, providing effective surface protection up to 1300°C. Sheet resistance measurements indicate that higher annealing temperatures and optimized spike annealing conditions improve dopant activation, with the lowest sheet resistance of 188 Ω/□ achieved at 1400°C using a two-spike process. These findings provide insights into optimizing thermal processes for high-performance GaN device fabrication.

Keywords:

rapid thermal annealing, spike annealing, ion implantation, sheet resistance, dopant activation, GaN

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