M. Meneghini^1,2, M. Fregolent¹, N. Zagni³, Y. Hamadoui⁴, A. Marcuzzi¹, D. Favero¹, C. De Santi¹, M. Buffolo^1,2, M. Tomasi¹, G. Zappalà¹, E. Bahat-Treidel⁵, E. Brusaterra⁵, F. Brunner⁵, O. Hilt⁵, C. Huber⁶, F. Medjdoub⁴, G. Meneghesso¹, G. Verzellesi³, P. Pavan³, and E. Zanoni¹

Published in:

IEEE International Electron Devices Meeting (IEDM 2024), San Francisco, USA, Dec. 7-11, ISBN 979-8-3503-6542-9 (2024).

Abstract:

We discuss recent advancements in the development of vertical GaN devices, and the related reliability challenges. Key results indicate that: (i) vertical GaN devices can show high performance, low background doping, and kV-range breakdown voltages; avalanche capability (a property of Si and SiC devices) is demonstrated also for vertical devices on silicon substrate, enabling reliable high-voltage operation; (ii) threshold voltage instabilities are related to the presence of interface and border traps, whose contribution can be modeled with great accuracy by prior characterization of the trap distribution profile; (iii) gate stack reliability is mainly limited by oxide breakdown; factors limiting off-state failure are discussed. Strategies for device improvement are proposed, also based on the learnings from silicon and silicon carbide technology.

Keywords:

MOSFET, Voltage measurement, Silicon carbide, Logic gates, Threshold voltage, Silicon, Mathematical models, Data models, Substrates, Stress

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