A Highly Efficient Reconfigurable All-Digital DLL-Based RF Transmitter Using Phase Interpolation in 22 nm FDSOI

P. Nickel^†∗, D. Sun^§∗, R. Staub^†, J. Kellermann^†, A. Wentzel^§ and F. Gerfers^†

Published in:

IEEE International Symposium on Circuits and Systems (ISCAS 2026), Shanghai, China, May 24-28, pp. 130-134 (2026).

Abstract:

This paper presents a digital RF transmitter (TX) for handset applications in 22nm CMOS FDSOI technology. The TX integrates an amplitude–phase interpolation estimator (APIE) that requires only two solvers, significantly reducing complexity, area, and power consumption. The TX enables digital pre-distortion (DPD) through its look-up table (LUT)-based amplitude modulator. It further incorporates a delay locked loop (DLL)-based pulse generator and a Class-D power amplifier (PA), delivering a maximum output power of 15.4dBm with a peak power-added efficiency (PAE) of 58.5% and a digital power consumption of only 28.7mW from a 900mV supply. Transistor level simulations demonstrate an adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) better than 43dB and −32dB respectively, transmitting an average output power of 8.5 dBm with 20MHz modulation bandwidth at 2GHz carrier frequency. Furthermore, the TX supports wideband orthogonal frequency-division multiplexing (OFDM) signals with bandwidths of 100 and 240MHz, maintaining ACLR levels of 32.2 and 25.3dB each. The demonstrated performance highlights the capability of the proposed transmitter to meet the stringent requirements of 5G and beyond while achieving excellent energy efficiency.

^† Chair of Mixed Signal Circuit Design, Technische Universität Berlin, Berlin, Germany
^§ Ferdinand-Braun-Institut (FBH), Berlin, Germany
^∗ These authors contributed equally to this work

Index Terms:

Digital Delta Sigma Modulator, Wireless Transmitter, CMOS Power Amplifier, RFPWM, Phase Modulation, DLL, FDSOI, Class-D, LUT

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