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Dynamic RD Modeling by Exploiting Gate Current Dependency of Virtual Gate Effect

P. Beleniotis1, C. Zervos1, F. Schnieder2, M. Rudolph1,2

Published in:

Proc. 18th European Microwave Integrated Circuits Conference (EuMIC 2023), Berlin, Germany, Sep. 18-19, ISBN: 978-2-87487-073-6, pp. 25-28 (2023).


This paper proposes a new method for compact modeling the virtual gate effect by adapting the gate current in the extraction procedure. Drain resistance (RD) of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) is dynamically varied by time-dependent trapping effects, demanding a high number of measurements for its accurate modeling in scaling-based drain-lag models. We implement insights from physical analysis of the virtual gate effect to make the extraction more efficient and trustworthy. The dynamic RD extraction is based on a simple dc gate current measurement to emulate its cumbersome nonlinear relation with the drain to source voltage (VDS). RF large-signal simulations with various cases of RD modeling are compared, confirming the accuracy of the presented method.

1 Brandenburg University of Technology Cottbus-Senftenberg (BTU)
2 Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik, Germany


GaN HEMT, trapping effects, gate current, compact model, microwave.

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