Fabrication technology of GaN/AlGaN HEMT slanted sidewall gates using thermally reflowed ZEP resist and CHF3/SF6 plasma etching

K.Y. Osipov, W. John, N. Kemf, S.A. Chevtchenko, P. Kurpas, M. Matalla, O. Krüger, and J. Würfl

Published in:

Int. Conf. on Compound Semiconductor Manufacturing Technology (CS ManTech 2013), New Orleans, USA, May 13-16, paper 041 (2013).

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In this work we present a technology of slanted sidewall gate fabrication using ICP etching of the SiNx passivation layer with a thermally reflowed ZEP 520A electron beam resist as etch mask. The influences of reflow time and temperature on structure size and sidewall angle are studied. Furthermore, the dependencies of SiNx etch rate, RF bias level, and etching selec-tivity of the SiNx/ZEP mask on process parameters are deter-mined. A bulk SiNx etch rate of ≈118 nm/min at an extremely low RF bias level of 8 V has been obtained. At these conditions SiNx/ZEPmask selectivity is 2.5. Gate lengths of 50 to 250 nm at a gate foot sidewall slope of 70° have been demonstrated. Test transistors fabricated on 3" GaN/AlGaN-sapphire wafers show reproducible 50 nm and 100 nm gates with high yield.

Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik, Gustav-Kirchhoff-Straße 4, 12489 Berlin, Germany


SiNx etch, ZEP 520A, GaN HEMT, Deep submicron gates