F. Buballa^*, S. Linnhoff^*, A. Wentzel^#, E. Wittenhagen^*, T. Hoffmann^#, W. Heinrich^#, F. Gerfers^*

Published in:

IEEE MTT-S Int. Microw. Symp. Dig., San Francisco, USA, Jun. 15-20, ISBN 979-8-3315-1409-9, pp. 320-323 (2025).

Abstract:

The paper presents a highly power efficient push-pull LDMOS-based pre-driver, implemented in a 22 nm FDSOI CMOS process, generating an output voltage swing of 6V for GaN-based switching power amplifier with an estimated capacitive load impedance of 0.35 pF. This is achieved by utilizing monolithical integrated LDMOS devices with a breakdown voltage of 6.5V, available in this deep sub micron state-of-the-art CMOS process, which are driven by an inverter-chain consisting of 2V thick-oxide devices with an active back-gate control, allowing duty-cycle adjustments to optimize the drivers efficiency. With a power consumption of 355 mW from a triple 2V, 4V and 6V power supply and a core area of 0.035 mm², a costand power-efficient alternative to typically utilized SiGe or integrated GaN solutions is presented. The proposed design was manufactured and bonded to a GaN MMIC to enable system performance evaluation. Achieving an error-free eye diagram with BER <10^-18 at the GaN MMIC output for data rates up to 4.3 GBaud.

Keywords:

driver, 22nm FDSOI, LDMOS, back-gate, GaN, gate driver, power amplifier, high-swing.

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