Modeling the Virtual Gate Voltage in Dispersive GaN HEMTs
P. Luo1,2, F. Schnieder1, O. Bengtsson1, W. Heinrich1 and M. Rudolph1,2
Published in:
IEEE MTT-S Int. Microw. Symp. Dig., Philadelphia, USA, Jun. 10-15, pp. 728-731 (2018).
Abstract:
The main contribution of this paper is to present a direct solution to model the virtual gate voltage describing GaN HEMT dispersion. This virtual gate voltage is related to a fitting parameter, which links the traps to present and past voltages. It is shown that the complexity of this trap-controlled parameter with respect to the bias is almost impossible to capture. For simplicity, three simple functions are proposed to describe its bias-dependence, and it is found that the choice of a proper function enables a significant improvement in modeling accuracy of the transistor large-signal behavior.
1 Brandenburg University of Technology (BTU), Ulrich L. Rohde Chair of RF and Microwave Techniques, Siemens-Halske-Ring 14, 03046 Cottbus, Germany
2 Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik (FBH), Gustav-Kirchhoff-Straße 4, 12489 Berlin, Germany
Index Terms:
GaN HEMT modeling, Chalmers model, trapping effects, drain lag, pulsed S-parameter measurements.
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