S.A. Chevtchenko, P. Kurpas, N. Chaturvedi, R. Lossy and J. Würfl

Published in:

Int. Conf. on Compound Semiconductor Manufacturing Technology (CS ManTech 2011), Palm Springs, USA, May 16-19, pp. 237-240 (2011).

Abstract:

The leakage current in AlGaN/GaN HFETs associated with gate encapsulation have been found to be sensitive to processing sequence and transistor layout. The main effect of the encapsulation by SiN_x is an increase in the off-state gate leakage currents, which reach values in 1×10^-3 A/mm range or higher. Based on the comparison of transistors having different layout the effect is attributed to a residual stress in the encapsulating dielectric layer. The resulting differences in the gate leakage for different types of transistors were measured up to four orders of magnitude. The lowest values were obtained for transistor type, which has openings in both layers of SiN_x formed in one etching step. The best average on-wafer value obtained in experiment is 3.0×10^-8 A/mm with standard deviation of 8.1×10^-9 A/mm. The optimized transistor layout and processing sequence has been used in our standard process for discrete GaN power transistors and MMICs. The results demonstrate stability and reproducibility of the developed approach.

Keywords:

AlGaN/GaN HFET, HEMT, dielectric passivation, leakage current

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