M. Rudolph, and R. Doerner

Published in:

IEEE Trans. Electron Dev., vol. 52, no. 9, pp. 1969-1975 (2005).

Abstract:

This paper investigates how time delays and capacitances observed under small-signal conditions can be consistently accounted for in heterojunction bipolar transistor (HBT) large-signal models. The approach starts at the circuit level by mapping the large-signal equivalent circuit (which consists of charge and current sources) to the well-known small-signal circuit (which consists of capacitances, transit-time, and resistances). It is shown that and how bias dependent charge sources at either pn-junction impact transit-time, base-collector capacitance, and their mutual dependence. It is demonstrated for the example of a GaAs-based HBT that the interrelation of the elements is observed in measurements as predicted. The results of the investigation enhance understanding of HBT model characteristics and provide a criterion to check model consistency. This paper identifies possible numerical instabilities

Index Terms:

Equivalent circuit, heterojunction bipolar transistor (HBT), semiconductor device modeling.

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