60 GHz Power Amplifier Utilizing 90 nm CMOS Technology
A. Hamidian1, V. Subramanian1, R. Doerner2 , R. Shu1, A. Malignaggi1, M.K. Ali1, G. Boeck1
Published in:
IEEE International Symposium on Radio-Frequency Integration Technology (RFIT 2011), Beijing, China, Nov. 30-Dec. 2, pp. 73-76 (2011).
Abstract:
This paper presents a fully integrated 60 GHz two stage power amplifier for wireless applications using common source topology and power combining. The PA is implemented in a 90 nm low power CMOS technology. The output power of the amplifier has been improved with the help of Wilkinson power combining technique. Also the Wilkinson power combiner has been utilized as a part of input and output matching networks to match the 16 Ω at the terminals of the power amplifier to 50 Ω at the output of the Wilkinson network. At 60 GHz the power amplifier achieves 11 dBm saturation output power, 9 dBm output power at 1dB gain compression point and more than 8 dB small signal gain with a peak power added efficiency of 6%. The broadband performance of the gain has been achieved utilizing the cascaded structures. The matching networks are based on high quality factor shielded coplanar transmission lines and fixed 300 fF MIM-capacitors. The detailed design procedure and the achieved measurement results are presented in this work.
1 Microwave Engineering Lab, Berlin Institute of Technology, Berlin, Germany
2 Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik, Gustav-Kirchhoff-Strasse 4, 12489 Berlin, Germany
Index Terms:
60 GHz, CMOS technology, Power amplifier, High data rate wireless applications.
© Copyright 2011 IEEE - All Rights Reserved. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Full version in pdf-format.